Container capacitors are well known in the art of semiconductor processing, and are particularly well known as a capacitor structure used in dynamic random access memories (DRAMs). A basic DRAM cell is schematically shown in FIG. 1A, and a cross section of a few of such cells is shown in FIG. 1B. The cross section of FIG. 1B shows only the basic features of a DRAM cell and for simplicity omits many details and processes steps which are well known in the art. As is known, two adjacent cells share a common bit line (BL) 12 which as shown constitutes a doped region of the silicon substrate 10. Each cell contains a word line (WL) 14 which constitutes the access transistor for the cell by coupling the bit line 12 to another doped region 16 of the silicon. This doped region 16 is connected to a container capacitor 18 via a polysilicon plug 17. The capacitor 18 is typically comprised of two layers 19, 20 of polysilicon, one of which (20) forms a “plate” with a voltage (Vplate) common to all of the capacitors 18. The layers 19, 20 are separated by a dielectric 21.
The container capacitors 18 are generally formed by etching a hole in the dielectric 22 (typically, a silicon dioxide or “oxide”) that overcoats the word lines 14 to expose plugs 17. This hole may extend over the word lines 14, but this is not shown for simplicity. A first layer of polysilicon (or “poly”) 19 is deposited within the hole and planarized or patterned to form a “U” shape in cross section, and which in three dimensions would resemble a “cup” or a “box” with an open top. The capacitor dielectric 21 (e.g., oxide, silicon nitride (“nitride”), silicon oxynitride (“oxynitride”), or any combination of these) is formed, and the second layer of poly 20 is deposited. After these processing steps, the original hole in the dielectric 22 may be completely filled by the poly 20, or may subsequently be intentionally filled by another dielectric layer (not shown).
A container capacitor 18 helps to increase the density of the cells in a DRAM because the capacitors are three-dimensional rather than planar, hence allowing a larger area capacitor in a smaller two-dimensional “footprint” on the silicon 10. However, as fabrication technologies advance, and as structures are made of smaller dimensions and at higher densities, the capacitors 18 can be affected. Smaller capacitor sizes equate to lower capacitances, and hence lower amounts of charge the capacitor can store. Accordingly, and again as a general matter, the sizes of the capacitors in DRAM cell are formed relatively large when compared to other structures of the cell to achieve a suitable capacitance. (Of course, other parameters such as dielectric thickness and dielectric constant also affect capacitance). But relatively large capacitors are disadvantageous to the density and/or area of the overall cell. Attempts to make suitably capacitive container capacitors larger by making them narrower but deeper can be difficult to pattern and etch, and require lithography alignments that can be difficult to achieve. As such, container capacitors can constitute a limiting factor in DRAM cell design. Thus, the art would be benefited by an improved design for such container capacitors, and specifically would be benefited by container capacitor structures that provide suitable capacitances, are easy to fabricate, do not require leading-edge line width processing and alignment, and which take up a limited two-dimensional footprint relative to the silicon substrate. This disclosure presents solutions.